The original version provided by Wzebra author Gunnar Andersson, I can't remember the WZEBRA homepage
http://www.nada.kth.se/~gunnar/othello.html has not been accessed, I will not pay attention to Wzebra for a long time. Using Bitboard technology and MMX instructions, this is the original version (GCC assembly), which must be compiled in GCC. The author said that I didn't like the VC's compilation format (exactly what Intel's habit), saying the truth, we don't adapt to GCC's compilation habits, 嘿嘿The first stuff seen in the glasses is a hippo, he will recognize the Horses to do Dad, 嘎嘎 ~~
Gunnar Andersson introduction text:
Bitboard trickery
Zebra's endgame solver is very fast, maybe the fastest around. One reason for this is that it represents the Othello board as four 32-bit words, two words for the black discs and two words for the white discs. Using this representation it is possible to write a very fast move generation functions. The fastest-first heuristics used for move ordering benefits from this as well, here you find a C assembly function that computes the number of legal moves for one player in less than 200 clock cycles on an AMD Athlon - I Have Not Timed It On Other Platforms, ON A Pentium III I Expect The Cycle Count To Be Roughly The Same, Whereas On a Pentium IV My Guess Is That Needs 300-400 CYCLES.
The code is used as follows: Call init_mmx () to initialize some constants (you only have to call this function once), then use bitboard_mobility () to get the mobility The code can be compiled as C code using GCC's asm extension It.. Is StraightForward But Boring to Convert It Into Code That Can Be Compiled Using Microsoft Visual C .
The main trick used by the code is to find all moves that flip discs in a certain direction, eg up, in parallel. This can be done in several different ways, this code uses a variation first suggested by Richard Delorme which I have improved somewhat . There are 8 possible flip directions, 6 of these are managed by the MMX ALUs and the remaining 2 by the integer ALUs.Currently the code averages about 2 instructions per clock cycle on an AMD Athlon - 400 instructions in 200 cycles Using the processor. optimally it should be possible to execute 3 instructions per clock cycle For this application it may be impossible to attain the theoretical optimum, but it almost certainly is possible to improve on my code by considering pairing and register stalls throughout -. I am a novice assembly programmer and have probably introduced lots of unnecessary stalls. It is possible to make it slightly faster by using the psadbw instruction which is available on Pentium III, Pentium IV, and Athlon. If y Ou can Optimize the code in any other way, please let me know.source:
/ *
CopyRight (C) 2003, Gunnar Andersson
All rights reserved.
Redistribution and use in source and binary forms, with or
WITHOUT MODIFICATION, Are Permitted Provided That
FOLLOWING CONDitions Are Met:
* Redistributions of Source Code Must Retain The Above Copyright Notice,
This List of conditions and the folowing disclaimer.
* Redistributions in Binary Form Must Reproduce The Above Copyright NOTICE,
This List of conditions and the folloading discuClaimer in the documentation
And / or Other Materials Provided with the distribution.
This Software Is Provided by The Copyright Holders and Contributors "AS"
And Any Express or Implied Warranties, Including, But Not Limited to, The Implied Warranties of Merchantability and Fitness for a Particular
Purpose Are Disclaimed. In No Event Shall The Copyright Owner OR Contributors
BE LIABLE for Any Direct, Indirect, Incidental, Special, Exemplary, OR
Consequential Damages (Including, But Not Limited to, Procurement of
Substitution Goods Or Services; Loss of Use, Data, or Business
Interruption) However Caused and On Any THEORY OF LIABILITY, WHETHER IN
Contract, Strict Liability, or Tort (Including NEGLIGENCE OtherWise)
Arising in any way out of the use of this software, even if advised of
The Possibility of Such Damage.
* /
Typedef struct {
Unsigned long high;
Unsigned long low;
} Bitboard;
Static unsigned long long Dir_mask0;
Static unsigned long long Dir_mask1;
Static Unsigned long long Dir_mask2;
Static unsigned long long Dir_mask3;
Static Unsigned long long_mask4;
Static unsigned long long Dir_mask5;
Static unsigned long long Dir_mask6;
Static unsigned long long Dir_mask7;
Static unsigned long long c0f;
Static unsigned long long c33;
Static unsigned long long c55;
Void
INIT_MMX (Void) {
Dir_mask0 = 0x007E7E7E7E7E7E00 ELL;
Dir_mask1 = 0x00fffffffffffffffff00 ELL;
Dir_mask2 = 0x007e7e7e7e7e7e00ull;
Dir_mask3 = 0x7e7e7e7e7e7e7e7e1;
Dir_mask4 = 0x7e7e7e7e7e7e7e7e1;
Dir_mask5 = 0x007e7e7e7e7e7e00ull;
Dir_mask6 = 0x00fffffffffffffffff00ull;
Dir_mask7 = 0x007e7e7e7e7e7e00ull;
C0F = 0x0F0F0F0F0F0F0F0FULL;
C33 = 0x333333333333333333333333333311;
c55 = 0x5555555555555555ULL;
}
int
Bitboard_mobility (const bitboard my_bits,
const bitboard opp_bits) {
Unsigned int count;
ASM Volatile
"MOVD %% EBX, %% MM0 / N / T" "PSLLQ $ 32, %% MM0 / N / T"
"MOVD %% ECX, %% MM3 / N / T"
"POR %% MM3, %% MM0 / N / T"
"MOVD %% EDI, %% MM1 / N / T"
"PSLLQ $ 32, %% MM1 / N / T"
"MOVD %% ESI, %% MM4 / N / T"
"POR %% MM4, %% MM1 / N / T"
"PXOR %% MM2, %% MM2 / N / T"
/ * shift = -9 rowdelta = -1 coldelta = -1 * /
/ * shift = 9 rowdelta = 1 Coldelta = 1 * /
/ * DISC # 1, Flip Direction 0. * /
/ * DISC # 1, Flip Direction 7. * /
"MOVQ %% MM1, %% MM3 / N / T"
"MOVQ %% MM0, %% MM4 / N / T"
"MOVQ %% MM0, %% MM6 / N / T"
"Pand _Dir_mask0, %% MM3 / N / T"
"pushl %% ESI / N / T"
"PSLLQ $ 9, %% MM4 / N / T"
"PSRLQ $ 9, %% MM6 / N / T"
"Pushl %% EDI / N / T"
"PAND %% MM3, %% MM4 / N / T"
"PAND %% MM3, %% MM6 / N / T"
"push %% ECX / N / T"
/ * DISC # 2, Flip Direction 0. * /
/ * DISC # 2, Flip Direction 7. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"PSLLQ $ 9, %% MM5 / N / T"
"PSRLQ $ 9, %% MM7 / N / T"
"pushl %% EBX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"And1 $ 2122219134, %% EDI / N / T"
"Andl $ 2122219134, %% ESI / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"SHLL $ 1, %% EBX / N / T"
"SHLL $ 1, %% ECX / N / T"
/ * Disc # 3, Flip Direction 0. * /
/ * DISC # 3, Flip Direction 7. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"ANDL %% EDI, %% EBX / N / T"
"ANDL %% ESI, %% ECX / N / T"
"PSLLQ $ 9, %% MM5 / N / T"
"PSRLQ $ 9, %% MM7 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"PAND %% MM3, %% MM5 / N / T" "PAND %% MM3, %% MM7 / N / T"
"SHLL $ 1, %% EDX / N / T"
"SHLL $ 1, %% EAX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
/ * DISC # 4, Flip Direction 0. * /
/ * Disc # 4, Flip Direction 7. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PSLLQ $ 9, %% MM5 / N / T"
"PSRLQ $ 9, %% MM7 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"SHLL $ 1, %% EDX / N / T"
"SHLL $ 1, %% EAX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
/ * Disc # 5, Flip Direction 0. * /
/ * DISC # 5, Flip Direction 7. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PSLLQ $ 9, %% MM5 / N / T"
"PSRLQ $ 9, %% MM7 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"SHLL $ 1, %% EDX / N / T"
"SHLL $ 1, %% EAX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
/ * DISC # 6, Flip Direction 0. * /
/ * DISC # 6, Flip Direction 7. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PSRLQ $ 9, %% MM7 / N / T"
"PSLLQ $ 9, %% MM5 / N / T" "MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"SHLL $ 1, %% EDX / N / T"
"SHLL $ 1, %% EAX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
"PSLLQ $ 9, %% MM4 / N / T"
"PSRLQ $ 9, %% MM6 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"POR %% MM4, %% MM2 / N / T"
"POR %% MM6, %% MM2 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
/ * shift = -8 rowdelta = -1 coldelta = 0 * /
/ * Shift = 8 rowdelta = 1 Coldelta = 0 * /
/ * Disc # 1, Flip Direction 1. * /
/ * Disc # 1, Flip Direction 6. * /
"MOVQ %% MM1, %% MM3 / N / T"
"MOVQ %% MM0, %% MM4 / N / T"
"MOVQ %% MM0, %% MM6 / N / T"
"pand _dir_mask1, %% mm3 / n / t"
"PSLLQ $ 8, %% MM4 / N / T"
"PSRLQ $ 8, %% MM6 / N / T"
"SHLL $ 1, %% EDX / N / T"
"SHLL $ 1, %% EAX / N / T"
"PAND %% MM3, %% MM4 / N / T"
"PAND %% MM3, %% MM6 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
/ * DISC # 2, FLIP DIRECTION 1. * /
/ * Disc # 2, Flip Direction 6. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PSLLQ $ 8, %% MM5 / N / T"
"PSRLQ $ 8, %% MM7 / N / T"
"SHLL $ 1, %% EBX / N / T"
"SHLL $ 1, %% ECX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
/ * Serialize Here: Add horizontal shl flips. * / "MOVD %% EBX, %% MM5 / N / T"
"PSLLQ $ 32, %% MM5 / N / T"
"MOVD %% ECX, %% MM7 / N / T"
"POR %% MM7, %% MM5 / N / T"
"POR %% MM5, %% MM2 / N / T"
/ * Disc # 3, FLIP DIRECTION 1. * /
/ * Disc # 3, FLIP DIRECTION 6. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"PSLLQ $ 8, %% MM5 / N / T"
"PSRLQ $ 8, %% MM7 / N / T"
"POPL %% EBX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"POPL %% ECX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"push %% ECX / N / T"
/ * Disc # 4, Flip Direction 1. * /
/ * Disc # 4, Flip Direction 6. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"pushl %% EBX / N / T"
"PSLLQ $ 8, %% MM5 / N / T"
"PSRLQ $ 8, %% MM7 / N / T"
"SHRL $ 1, %% EBX / N / T"
"SHRL $ 1, %% ECX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"ANDL %% EDI, %% EBX / N / T"
"ANDL %% ESI, %% ECX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
/ * Disc # 5, Flip Direction 1. * /
/ * Disc # 5, FLIP DIRECTION 6. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"PSLLQ $ 8, %% MM5 / N / T"
"PSRLQ $ 8, %% MM7 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"SHRL $ 1, %% EAX / N / T"
"SHRL $ 1, %% EDX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
/ * Disc # 6, Flip Direction 1. * /
/ * DISC # 6, Flip Direction 6. * / "MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PSLLQ $ 8, %% MM5 / N / T"
"PSRLQ $ 8, %% MM7 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"SHRL $ 1, %% EAX / N / T"
"SHRL $ 1, %% EDX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
"PSLLQ $ 8, %% MM4 / N / T"
"PSRLQ $ 8, %% MM6 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"POR %% MM4, %% MM2 / N / T"
"POR %% MM6, %% MM2 / N / T"
/ * shift = -7 rowdelta = -1 coldelta = 1 * /
/ * Shift = 7 rowdelta = 1 Coldelta = -1 * /
/ * Disc # 1, Flip Direction 2. * /
/ * Disc # 1, Flip Direction 5. * /
"MOVQ %% MM1, %% MM3 / N / T"
"MOVQ %% MM0, %% MM4 / N / T"
"MOVQ %% MM0, %% MM6 / N / T"
"pand _dir_mask2, %% mm3 / n / t"
"PSLLQ $ 7, %% MM4 / N / T"
"PSRLQ $ 7, %% MM6 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"PAND %% MM3, %% MM4 / N / T"
"PAND %% MM3, %% MM6 / N / T"
"SHRL $ 1, %% EAX / N / T"
"SHRL $ 1, %% EDX / N / T"
/ * DISC # 2, Flip Direction 2. * /
/ * DISC # 2, Flip Direction 5. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
"PSLLQ $ 7, %% MM5 / N / T"
"PSRLQ $ 7, %% MM7 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PAND %% MM3, %% MM5 / N / T" "PAND %% MM3, %% MM7 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"SHRL $ 1, %% EAX / N / T"
"SHRL $ 1, %% EDX / N / T"
/ * DISC # 3, Flip Direction 2. * /
/ * DISC # 3, FLIP DIRECTION 5. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
"PSLLQ $ 7, %% MM5 / N / T"
"PSRLQ $ 7, %% MM7 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"SHRL $ 1, %% EAX / N / T"
"SHRL $ 1, %% EDX / N / T"
/ * Disc # 4, Flip Direction 2. * /
/ * DISC # 4, Flip Direction 5. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
"PSLLQ $ 7, %% MM5 / N / T"
"PSRLQ $ 7, %% MM7 / N / T"
"Orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"MOVL %% EBX, %% EAX / N / T"
"MOVL %% ECX, %% EDX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"SHRL $ 1, %% EAX / N / T"
"SHRL $ 1, %% EDX / N / T"
/ * DISC # 5, Flip Direction 2. * /
/ * Disc # 5, Flip Direction 5. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"ANDL %% EDI, %% EAX / N / T"
"ANDL %% ESI, %% EDX / N / T"
"PSLLQ $ 7, %% MM5 / N / T"
"PSRLQ $ 7, %% MM7 / N / T" "orl %% EAX, %% EBX / N / T"
"Orl %% EDX, %% ECX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"SHRL $ 1, %% EBX / N / T"
"SHRL $ 1, %% ECX / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
/ * Serialize Here: add horizontal shr flips. * /
"MOVD %% EBX, %% MM5 / N / T"
"PSLLQ $ 32, %% MM5 / N / T"
"MOVD %% ECX, %% MM7 / N / T"
"POR %% MM7, %% MM5 / N / T"
"POR %% MM5, %% MM2 / N / T"
"POPL %% EBX / N / T"
/ * Disc # 6, Flip Direction 2. * /
/ * Disc # 6, Flip Direction 5. * /
"MOVQ %% MM4, %% MM5 / N / T"
"MOVQ %% MM6, %% MM7 / N / T"
"PSLLQ $ 7, %% MM5 / N / T"
"PSRLQ $ 7, %% MM7 / N / T"
"POPL %% ECX / N / T"
"PAND %% MM3, %% MM5 / N / T"
"PAND %% MM3, %% MM7 / N / T"
"POPL %% EDI / N / T"
"POR %% MM5, %% MM4 / N / T"
"POR %% MM7, %% MM6 / N / T"
"POPL %% ESI / N / T"
"PSLLQ $ 7, %% MM4 / N / T"
"PSRLQ $ 7, %% MM6 / N / T"
"POR %% MM4, %% MM2 / N / T"
"POR %% MM6, %% MM2 / N / T"
/ * mm2 is the pseudo-feasible moves at this point. * /
/ * Let mm7 be the feasible moves, i.e., mm2 restricted to Empty Squares. * /
"MOVQ %% MM0, %% MM7 / N / T"
"POR %% MM1, %% MM7 / N / T"
"Pandn %% MM2, %% MM7 / N / T"
/ * Count The Moves, I., The Number of Bits Set in mm7. * /
"MOVQ %% MM7, %% MM1 / N / T"
"PSRLD $ 1, %% MM7 / N / T"
"Pand _C55, %% MM7 / N / T"
"PSUBD %% MM7, %% MM1 / N / T"
"MOVQ %% MM1, %% MM7 / N / T"
"PSRLD $ 2, %% MM1 / N / T"
"Pand _C33, %% MM7 / N / T"
"Pand _C33, %% MM1 / N / T"
"PADDD %% MM1, %% MM7 / N / T"
"MOVQ %% MM7, %% MM1 / N / T"
"PSRLD $ 4, %% MM7 / N / T" "PADDD %% MM1, %% MM7 / N / T"
"pand _c0f, %% MM7 / N / T"
"MOVQ %% MM7, %% MM1 / N / T"
"PSRLD $ 8, %% MM7 / N / T"
"PADDD %% MM1, %% MM7 / N / T"
"MOVQ %% MM7, %% MM1 / N / T"
"PSRLD $ 16, %% MM7 / N / T"
"PADDD %% MM1, %% MM7 / N / T"
"MOVQ %% MM7, %% MM1 / N / T"
"PSRLQ $ 32, %% MM7 / N / T"
"PADDD %% MM1, %% MM7 / N / T"
"MOVD %% MM7, %% EAX / N / T"
"Andl $ 63, %% EAX / N / T"
/ * RESET the fp / mmx unit. * /
"EMMS / N"
: "= a" (count)
: "B" (my_bits.high), "c" (my_bits.low), "D" (OPP_BITS.HIGH), "S" (OPP_BITS.LOW));
Return count;
}
